Classic Moore’s Law Scaling Challenges Demand New Ways to Wire and Integrate Chips

As classic 2D scaling with EUV shrinks on-chip wiring, electrical resistance increases exponentially, creating power, performance and heat challenges. Moreover, as transistor counts continue to increase exponentially while 2D scaling slows, die sizes are increasing to the point where designers are hitting the “reticle limit” of chip designs. Fortunately, innovations in chip wiring will enable chipmakers to continue delivering improvements in performance and power—while advances in chip integration will give designers virtually unlimited transistor budgets. In short, “new ways to wire and integrate chips” will enable amazing computing experiences for everyone.

Newer Ways to Shrink

The industry will continue to use EUV lithography and materials engineering to push logic density scaling to the limit. In recent years, DTCO techniques have supplemented classic 2D scaling, and today, these “newer ways to shrink” contribute about half of the industry’s progress.

WFE Intensity Step-up: 3D NAND Case Study

We’ve received great feedback on our “Battle of Exponentials” framework, which examines the market impacts we’ve observed since around 2015 as data generation continued to expand at an exponential rate while classic Moore’s Law scaling slowed. In this blog post we focus on the step-up in NAND equipment capital intensity that occurred during the transition from 2D to 3D NAND architectures.